For flip-chip, multi-layer IC devices, debugging for defects in the IC is difficult due to having to approach the desired layers from the backside of the device. FIG. 1 illustrates a sideview block diagram of a typical flip-chip configuration. As shown in FIG. 1, an IC device 10 is coupled to a ceramic package 12 (e.g., a C4 package) via solder bumps 14. The solder bumps 14 act as chip-to-carrier interconnects to attach the IC device 10 to the ceramic package 12 and to mate with corresponding pad patterns to form the necessary electrical contacts between the circuit(s) of the IC device 10 and pins of the package 12.
Testing of the circuit remains a challenge due to the upside-down nature of the flip-chip orientation. While the circuit may be approached through the backside layers, such techniques are usually not preferred due to the difficulties associated with having to access the layers in an unconventional order. Further, these techniques normally reduce the thickness of the device to reach the circuit, making the device extremely fragile and cumbersome to handle and utilize during testing.
Accordingly, a need exists for an efficient procedure for topside analysis of an IC mounted in a flip-chip orientation. The present invention addresses such a need.